Low Power Bus Encoding Techniques for Memory Testing

Power reduction during testing is one of the most important challenges for the VLSI design and test engineers. Switching is one of the important contributors to the power consumption of on chip buses. This paper addresses the problem of minimizing power dissipation due to switching of the busses during testing. For memory testing, many read/write cycles are required (as per March algorithm), in which test patterns are sent through the data bus, according to the addressing sequences. The address switching is also controlled by address encoding schemes with reference data. The result shows the average power reduction of 30% and 74.8% in data bus and addresses buses encoding schemes respectively.